IssueTracker

The Arm v8.1-m branch target identification feature (BTI) as described in https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension is the Microcontroller profile equivalent of the AArch64 branch target identification feature. Note that the AArch64 branch target identification which is used in production today is unaffected.

A subset of the indirect branches are classified as BTI setting. When the BTI feature is enabled these BTI setting branches can only target BTI clearing instructions, otherwise an INVSTATE usage fault is generated. This limits the number of JOP gadgets that an attacker can use.

We (Arm) have found a case where LLVM can select a non BTI setting branch instruction MOV PC, Rn which does not have to land on a BTI clearing instruction. If the attacker can control Rn they can bypass the BTI protection.

The specific problem is the lowering of ARM::t2BR_JT which can be used to implement jump tables expands to MOV PC, Rn in Arm v8.1-M rather than the BTI setting BX Rn. Note that this requires a very large switch statement as usually the TBH and TBB table branch instructions are used.

An example that we have made that places Rn under control of the attacker. Note that the __llvm_unreachable() is required for the compiler to elide the range check.

// File bti.c
int v;
 
// Attacker is assumed to control value of x
int *foo(int *x) {
  switch (*++x) {
  case 0:
    // A large amount of data to force an indirect branch.
    asm(".space 140000");
    v = 42;
    break;
  case 1:
    v = 1337;
    break;
  case 2:
    v = 15532;
    break;
  case 3:
    v = 1234;
    break;
  default:
    // User is telling compiler that all other values
    // are undefined behavior. Compiler determines that
    // a range check is unnecessary.
    __builtin_unreachable();
  }
  return x;
}

Results in:

foo:
        .fnstart
        bti
        ldr     r2, [r0, #4]!
        movw    r1, #1337
        adr.w   r3, .LJTI0_0
        add.w   r3, r3, r2, lsl #2 // r3 determined by base of jump table + attacker controlled offset
        mov     pc, r3 // non BTI setting branch to r3
        .p2align        2
.LJTI0_0:
        b.w     .LBB0_2
        b.w     .LBB0_5
        b.w     .LBB0_3
        b.w     .LBB0_4
        ...

The Arm v8.1-M BTI extension is not yet available in consumer hardware. The first CPU to support it is the Cortex-M85 due this year (https://www.renesas.com/eu/en/about/press-room/renesas-demonstrate-first-ai-implementations-arm-cortex-m85-processor-featuring-helium-technology). There is a possibility that software is being developed prior to the release.

We have a fix (use BX Rn) that we can upstream once we've checked if anyone is developing software for Arm v8.1-M